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HFA3861
ADVANCE INFORMATION
Data Sheet
July 1999
File Number
4699.1
Direct Sequence Spread Spectrum Baseband Processor
The Intersil HFA3861 Direct Sequence Spread Spectrum (DSSS) baseband processor is part of the PRISM(R) 2.4GHz radio chipset, and contains all the functions necessary for a full or half duplex packet baseband transceiver.
TM
Features
* Complete DSSS Baseband Processor * Processing Gain . . . . . . . . . . . . . . . . . . . . FCC Compliant * Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps * Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 10 x 10mm * Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V * Modulation Methods . . . . . . . . DBPSK, DQPSK, and CCK * Supports Full or Half Duplex Operations * On-Chip A/D and D/A Converters for I/Q Data (6-Bit, 22MSPS), AGC, and Adaptive Power Control (7-Bit) * Targeted for Multipath Delay Spreads ~100ns * Supports Short Preamble Acquisition
The HFA3861 has on-board A/D's for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates. Built-in flexibility allows the HFA3861 to be configured through a general purpose control bus, for a range of applications. Both Receive and Transmit AGC functions with 7-bit AGC control obtain maximum performance in the analog portions of the transceiver. The HFA3861 is housed in a thin plastic quad flat package (TQFP) suitable for PCMCIA board applications.
Applications
* Enterprise WLAN Systems * Systems Targeting IEEE 802.11 Standard * DSSS PCMCIA Wireless Transceiver * Spread Spectrum WLAN RF Modems
Ordering Information
PART NO. HFA3861IV HFA3861IV96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PKG. TYPE 64 Ld TQFP Tape and Reel PKG. NO. Q64.10x10
* TDMA Packet Protocol Radios * Part 15 Compliant Radio Links * Portable PDA/Notebook Computer * Wireless Digital Audio, Video, Multimedia
Pinout
SDI RESET TX_PE RX_PE CCA TX_RDY TXD VDDD GNDd TXCLK MD_RDY RXD RXCLK TEST7 TEST6 TEST5
* PCN/Wireless PBX * Wireless Bridges
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GNDd VDDD SD SCLK R/W CS GNDd VDDD GNDa RX_I+ RX_IVDDA RX_Q+ RX_QGNDa VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDDA TX_AGC_IN RX-IF_DET GNDa IREF VDDA TX_I+ TX_IGNDa COMPCAP2 COMPRES2 GNDa TX_Q+ TX_QVDDA COMPRES1 TEST4 TEST3 TEST2 TEST1 TEST0 GNDd MCLK NC ANT-SEL ANT-SEL RX-RF_AGC VDDD GNDd TX_IF_AGC RX_IF_AGC COMPCAP1
Simplified Block Diagram
ANT_SEL RX_RF_AGC RX_IF_DET RX_IF_AGC THRESH. DETECT IF DAC I ADC Q ADC VREF I/O TX_I I DAC TX_Q Q DAC TX_IF_AGC TX_AGC_IN 44MHz MCLK TX DAC TX ADC 6 6 MOD 1 1 7 AGC CTL
RX_I RX_Q
6 6 DEMOD
DATA I/O
7 6
TX ALC HFA 3861 BBP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 PRISM and PRISM logo are trademarks of Intersil Corporation.
HFA3861 Table of Contents
PAGE Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Port (4 Wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX I/Q A/D Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX_AGC_IN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX I/Q DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Header/Packet Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spread Spectrum Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Channel Assessment (CCA) and Energy Detect (ED) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PN Correlators Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Demodulation and Tracking Description (DBPSK and DQPSK Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Decoder and Descrambler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Demodulation in the CCK Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall Eb/N0 Versus BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier Offset Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thin Plastic Quad Flatpack Packages (TQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3 4 5 6 7 7 8 8 8 9 9 9 9 10 12 12 12 13 13 14 14 15 16 17 17 19 19 19 19 20 20 21 23 33 33 35
2
Typical Application Diagram
RF DAC RF ADC IF DAC HFA3683 RF/IF CONV REFOUT PLL RF LO HFA3963 RFPA REF IN REF IN HFA3783 QUAD IF TX DAC TX ADC REF IN PLL I/O LO IF LO I DAC Q DAC I ADC Q ADC
1 1 7 AGC CTL RADIO DATA INTERFACE WEP ENGINE HFA3841 MAC
I/O 6 6 MOD
RADIO CONTROL PORTS
7 6
TX ALC HFA3861 BBP
GP SERIAL PORTS
MEMORY ACCESS ARBITER
HOSTPC INTERFACE
3
44MHz MCLK DIFFERENTIAL SIGNALS
6 6 DEMOD
CPU 16-BIT PIPELINED CONTROL PROCESSOR
HOST INTERFACE LOGIC
HFA3861
EXTERNAL MEMORY
TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3861
For additional information on the PRISM(R) chip set, call (407) 724-7800 to access Intersil' AnswerFAX system. When prompted, key in the four-digit document number (File #) of the data sheets you wish to receive.
The four-digit file numbers are shown in the Typical Application Diagram, and correspond to the appropriate circuit.
HFA3861 Pin Descriptions
NAME VDDA (Analog) VDDD (Digital) GNDa (Analog) PIN 12, 17, 22, 31 2, 8, 37, 57 9, 15, 20, 25, 28, TYPE I/O Power Power Ground Ground I I I I O DESCRIPTION DC power supply 2.7V - 3.6V (Not Hard wired Together On Chip). DC power supply 2.7 - 3.6V DC power supply 2.7 - 3.6V, ground (Not Hard wired Together On Chip). DC power supply 2.7 - 3.6V, ground. Voltage reference for A/D's and D/A's Current reference for internal ADC and DAC devices. Requires a 12k resistor to ground. Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for differential drive of antenna switches. The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for differential drive of antenna switches. Analog input to the receive power A/D converter for AGC control. Analog drive to the IF AGC control. Drive to the RF AGC stage attenuator. CMOS digital. Input to the transmit power A/D converter for transmit AGC control. Analog drive to the transmit IF power control. When active, the transmitter is configured to be operational, otherwise the transmitter is in standby mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to the HFA3861. The rising edge of TX_PE will start the internal transmit state machine and the falling edge will initiate shut down of the state machine. TX_PE envelopes the transmit data except for the last bit. The transmitter will continue to run for 4s after TX_PE goes inactive to allow the PA to shut down gracefully. TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network processor to the HFA3861. The data is received serially with the LSB first. The data is clocked in the HFA3861 at the rising edge of TXCLK. TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to the HFA3861, synchronously. Transmit data on the TXD bus is clocked into the HFA3861 on the rising edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock will be dependent upon the data rate that is programmed in the signalling field of the header. TX_RDY is an output to the external network processor indicating that Preamble and Header information has been generated and that the HFA3861 is ready to receive the data packet from the network processor over the TXD serial bus. Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The CCA may be configured to one of four possible algorithms. The CCA algorithm and its features are described elsewhere in the data sheet. Logic 0 = Channel is clear to transmit. Logic 1 = Channel is NOT clear to transmit (busy). This polarity is programmable and can be inverted. RXD is an output to the external network processor transferring demodulated Header information and data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with MD_RDY. RXCLK is the bit clock output. This clock is used to transfer Header information and payload data through the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is held to a logic "0" state during the CRC16 reception. RXCLK becomes active after the SFD has been detected. Data should be sampled on the rising edge. This polarity is programmable and can be inverted.
GNDd (Digital) 1, 7, 36, 43, 56 VREF IREF RXI, +/RXQ, +/ANTSEL 16 21 10/11 13/14 39
ANTSEL
40
O
RX_IF_DET RX_IF_AGC RX_RF_AGC TX_AGC_IN TX_IF_AGC TX_PE
19 34 38 18 35 62
I O O I O I
TXD
58
I
TXCLK
55
O
TX_RDY
59
O
CCA
60
O
RXD
53
O
RXCLK
52
O
4
HFA3861 Pin Descriptions
NAME MD_RDY PIN 54 (Continued) TYPE I/O O DESCRIPTION MD_RDY is an output signal to the network processor, indicating header data and a data packet are ready to be transferred to the processor. MD_RDY is an active high signal that signals the start of data transfer over the RXD serial bus. MD_RDY goes active when the SFD (Note) is detected and returns to its inactive state when RX_PE goes inactive or an error is detected in the header. When active, the receiver is configured to be operational, otherwise the receiver is in standby mode. This is an active high input signal. In standby, RX_PE inactive, all RX A/D converters are disabled. SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the register address immediately followed by 8 more bits representing the data that needs to be written or read at that register. In the 4 wire interface mode, this pin is tristated unless the R/W pin is high. SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is 11MHz or one half the master clock frequency, whichever is lower. Serial Data Input in 3 wire mode described in Tech Brief TBD. This pin is not used in the 4 wire interface described in this data sheet. It should not be left floating. R/W is an input to the HFA3861 used to change the direction of the SD bus when reading or writing data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read while a low level is a write. CS is a Chip select for the device to activate the serial control port. The CS doesn't impact any of the other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low signal. When inactive SD, SCLK, and R/W become "don't care" signals. This is a data port that can be programmed to bring out internal signals or data for monitoring. These bits are primarily reserved by the manufacturer for testing. A further description of the test port is given in the appropriate section of this data sheet. Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the HFA3861 goes into the power standby mode. RESET does not alter any of the configuration register values nor does it preset any of the registers into default values. Device requires programming upon power-up. Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks. TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/ 24TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential 29+/30-. Compensation capacitor Compensation capacitor Compensation Resistor Compensation Resistor
RX_PE SD
61 3
I I/O
SCLK
4
I
SDI R/W
64 5
I I
CS
6
I
TEST 7:0
51, 50, 49, 48, 47, 46, 45, 44 63
I/O
RESET
I
MCLK TXI+/TXQ+/CompCap CompCap2 CompRes1 CompRes2
42 23/24 29/30 33 26 32 27
I O O I I I I
NOTE: See CR10<3>.
External Interfaces
There are three primary digital interface ports for the HFA3861 that are used for configuration and during normal operation of the device as shown in Figure 1. These ports are: * The Control Port, which is used to configure, write and/or read the status of the internal HFA3861 registers. * The TX Port, which is used to accept the data that needs to be transmitted from the network processor. * The RX Port, which is used to output the received demodulated data to the network processor. In addition to these primary digital interfaces the device includes a byte wide parallel Test Port which can be configured to output various internal signals and/or data. The device can also be set into various power consumption modes by external control. The HFA3861 contains four Analog to Digital (A/D) converters and four Digital to Analog converters. The analog interfaces to the HFA3861 include, the In phase (I) and quadrature (Q) data component inputs/ outputs, and the RF and IF receive automatic gain control and transmit output power control.
5
HFA3861
HFA3861 ANALOG INPUTS A/D REFERENCE POWER DOWN SIGNALS TEST PORT ANT_SEL 8 RXI RXQ AGC VREF IREF TX_PE RX_PE RESET TEST AGC TXI TXQ TXD TXCLK TX_RDY RXD RXC MD_RDY CS SD SCLK R/W SDI ANALOG OUTPUTS
TX_PORT
RX_PORT
CONTROL_PORT
FIGURE 1. EXTERNAL INTERFACES
Control Port (4 Wire)
The serial control port is used to serially write and read data to/from the device. This serial port can operate up to a 11MHz rate or 1/2 the maximum master clock rate of the device, MCLK (whichever is lower). MCLK must be running and RESET must be inactive during programming. This port is used to program and to read all internal registers. The first 8 bits always represent the address followed immediately by the 8 data bits for that register. The LSB of the address is a don't care, but reserved for future expansion. The serial transfers
are accomplished through the serial data pin (SD). SD is a bidirectional serial data bus. Chip Select (CS), and Read/Write (R/W) are also required as handshake signals for this port. The clock used in conjunction with the address and data on SD is SCLK. This clock is provided by the external source and it is an input to the HFA3861. The timing relationships of these signals are illustrated in Figures 2 and 3. R/W is high when data is to be read, and low when it is to be written. CS is an asynchronous reset to the state machine. CS must be active (low) during the entire data transfer cycle. CS selects the serial control port device only. The serial control port operates asynchronously from the TX and RX ports and it can accomplish data transfers independent of the activity at the other digital or analog ports. The HFA3861 has 96 internal registers that can be configured through the control port. These registers are listed in the Configuration and Control Internal Register table. Table 9 lists the configuration register number, a brief name describing the register, the HEX address to access each of the registers and typical values. The type indicates whether the corresponding register is Read only (R) or Read/Write (R/W). Some registers are two bytes wide as indicated on the table (high and low bytes).
7 SCLK
FIRST ADDRESS BIT 6 5 4 3 2
1
0
FIRST DATABIT OUT 7 6 5 4 3
2
1
0
SD
7 MSB
6
5
4
3
2
1
7 MSB
6
5
4
3
2
1
0 LSB
ADDRESS IN
DATA OUT
R/W CS
NOTES: 1. The HFA3861 always uses the rising edge of SCLK to sample address and data and to generate read data. 2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data. FIGURE 2. CONTROL PORT READ TIMING
7 SCLK SD 7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0 LSB
ADDRESS IN
DATA IN
R/W CS
FIGURE 3. CONTROL PORT WRITE TIMING
6
HFA3861 TX Port
The transmit data port accepts the data that needs to be transmitted serially from an external data source. The data is modulated and transmitted as soon as it is received from the external data source. The serial data is input to the HFA3861 through TXD using the next rising edge of TXCLK to clock it in the HFA3861. TXCLK is an output from the HFA3861. A timing scenario of the transmit signal handshakes and sequence is shown on timing diagram Figure 4. The external processor initiates the transmit sequence by asserting TX_PE. TX_PE envelopes the transmit data packet on TXD. The HFA3861 responds by generating a Preamble and Header. Before the last bit of the Header is sent, the HFA3861 begins generating TXCLK to input the serial data on TXD. TXCLK will run until TX_PE goes back to its inactive state indicating the end of the data packet. The user needs to hold TX_PE high for as many clocks as there bits to transmit. For the higher data rates, this will be in multiples of the number of bits per symbol. The HFA3861 will continue to output modulated signal for 4s after the last data bit is output, to supply bits to flush the modulation path. TX_PE must be held until the last data bit is output from the MAC/FIFO. The minimum TX_PE inactive pulse required to restart the preamble and header generation is 2.22s and to reset the modulator is 4.22s. The HFA3861 internally generates the preamble and header information from information supplied via the control registers. The external source needs to provide only the data portion of the packet and set the control registers. The timing diagram of this process is illustrated on Figure 4. Assertion of TX_PE will initialize the generation of the preamble and header. TX_RDY, which is an output from the HFA3861, is used (if needed) to indicate to the external processor that the preamble has been generated and the device is ready to receive the data packet (MPDU) to be transmitted from the external processor. Signals TX_RDY, TX_PE and TXCLK can be set individually, by programming Configuration Register (CR) 1, as either active high or active low signals. The transmit port is completely independent from the operation of the other interface ports including the RX port, therefore supporting a full duplex mode.
RX Port
The timing diagram Figure 5 illustrates the relationships between the various signals of the RX port. The receive data port serially outputs the demodulated data from RXD. The data is output as soon as it is demodulated by the HFA3861. RX_PE must be at its active state throughout the receive operation. When RX_PE is inactive the device's receive functions, including acquisition, will be in a stand by mode.
TXCLK
TX_PE
FIRST DATA BIT SAMPLED
LAST DATA BIT SAMPLED
TXD
LSB
DATA PACKET
MSB DEASSERTED WHEN LAST CHIP OF MPDU CLEARS MOD PATH OF 3861 EXCEPT FOR TX FILTER AND D/A
TX_RDY
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXCLK. FIGURE 4. TX PORT TIMING
RXCLK
RX_PE HEADER FIELDS PROCESSING PREAMBLE/HEADER DATA
MD_RDY
RXD
LSB
DATA PACKET
MSB
NOTE: MD_RDY active after CRC16. See detailed timing diagrams (Figures 18, 19, 20). FIGURE 5. RX PORT TIMING
7
HFA3861
RXCLK is an output from the HFA3861 and is the clock for the serial demodulated data on RXD. MD_RDY is an output from the HFA3861 and it may be set to go active after the SFD or CRC fields. Note that RXCLK becomes active after the Start Frame Delimiter (SFD) to clock out the Signal, Service, and Length fields, then goes inactive during the header CRC field. RXCLK becomes active again for the data. MD_RDY returns to its inactive state after RX_PE is deactivated by the external controller, or if a header error is detected. A header error is either a failure of the CRC check, or the failure of the received signal field to match one of the 4 programmed signal fields. For either type of header error, the HFA3861 will reset itself after reception of the CRC field. If MD_RDY had been set to go active after CRC, it will remain low. MD_RDY and RXCLK can be configured through CR 1, bits 1 and 0 to be active low, or active high. The receive port is completely independent from the operation of the other interface ports including the TX port, supporting therefore a full duplex mode. The voltages applied to pin 16, VREF and pin 21, IREF set the references for the internal I and Q A/D converters. In addition, For a nominal I/Q input of 250mVP-P, the suggested VREF voltage is 1.2V.
AGC Circuit
The AGC circuit is designed to optimize A/D performance for the I and Q inputs by maintaining the proper headroom on the 6-bit converters. There are two gain stages being controlled. At RF, the gain control is a 30dB step in gain from turning off the LNA. This RF gain control optimizes the receiver dynamic range when the signal level is high and maintains the noise figure of the receiver when it is needed most. At IF the gain control is linear and covers the bulk of the gain control range of the receiver. The AGC sensing mechanism uses a combination of the I and Q A/D converters and the detected signal level in the IF to determine the gain settings. The A/D outputs are monitored in the HFA3861 for the desired nominal level. When it is reached, by adjusting the receiver gain, the gain control is locked for the remainder of the packet.
RX I/Q A/D Interface
The PRISM baseband processor chip (HFA3861) includes two 6-bit Analog to Digital converters (A/Ds) that sample the balanced differential analog input from the IF down converter. The I/Q A/D clock, samples at twice the chip rate. The nominal sampling rate is 22MHz. The interface specifications for the I and Q A/Ds are listed in Table 1. The HFA3861 is designed to be DC coupled to the HFA3783.
TABLE 1. I, Q, A/D SPECIFICATIONS PARAMETER Full Scale Input Voltage (VP-P) Input Bandwidth (-0.5dB) Input Capacitance (pF) Input Impedance (DC) fS (Sampling Frequency) MIN 0.90 5k TYP 1.00 11MHz 2 22MHz MAX 1.10 -
RX_AGC_IN Interface
The signal level in the IF stage is monitored to determine when to impose the up to 30dB gain reduction in the RF stage. This maximizes the dynamic range of the receiver by keeping the RF stages out of saturation at high signal levels. When the IF circuits' sensor output reaches 0.5V, the HFA3861 comparator switches in the 30dB pad and compensates the IF AGC and RSSI measures.
RX_RF_AGC RX_IF_DET RX_IF_AGC RX_I HFA3683 HFA3783 RX_Q THRESH. DETECT IF DAC I ADC Q ADC
1 1 7 AGC CTL
6 6 DEMOD
DATA I/O I/O HFA3861
FIGURE 6. AGC CIRCUIT
8
HFA3861 TX I/Q DAC Interface
The transmit section outputs balanced differential analog signals from the transmit DACs to the HFA3783. These are DC coupled and digitally filtered. noise floor values. Optimum receiver operation may not be achieved until these values are reestablished (typically <20s of operation in noise only needed). The power savings of activating RESET must be weighed against this. Table 2 describes the power down modes available for the HFA3861 (VCC = 3.3V). The table values assume that all other inputs to the part (MCLK, SCLK, etc.) continue to run except as noted.
Test Port
The HFA3861 provides the capability to access a number of internal signals and/or data through the Test port, pins TEST 7:0. The test port is programmable through configuration register (CR 34). Any signal on the test port can also be read from configuration register (CR50) via the serial control port. Additionally, the transmit DACs can be configured to show signals in the receiver via CR 14. This allows visibility to analog like signals that would normally be very difficult to capture.
Transmitter Description
The HFA3861 transmitter is designed as a Direct Sequence Spread Spectrum Phase Shift Keying (DSSS PSK) modulator. It can handle data rates of up to 11Mbps (refer to AC and DC specifications). The various modes of the modulator are Differential Binary Phase Shift Keying (DBPSK) for 1Mbps, Differential Quaternary Phase Shift Keying (DQPSK) for 2Mbps, and Complementary Code Keying (CCK) for 5.5Mbps and 11Mbps. These implement data rates as shown in Table 3. The major functional blocks of the transmitter include a network processor interface, DPSK modulator, high rate modulator, a data scrambler and a spreader, as shown in Figure 7. CCK is essentially a quadra-phase form of M-ARY Orthogonal Keying. A description of that modulation can be found in Chapter 5 of: "Telecommunications System Engineering", by Lindsey and Simon, Prentis Hall publishing. The preamble is always transmitted as the DBPSK waveform while the header can be configured to be either DBPSK, or DQPSK, and data packets can be configured for DBPSK, DQPSK, or CCK. The preamble is used by the receiver to achieve initial PN synchronization while the header includes the necessary data fields of the communications protocol to establish the physical layer link. The transmitter generates the synchronization preamble and header and knows when to make the DBPSK to DQPSK or CCK switchover, as required.
Power Down Modes
The power consumption modes of the HFA3861 are controlled by the following control signals. Receiver Power Enable (RX_PE, pin 61), which disables the receiver when inactive. Transmitter Power Enable (TX_PE, pin 62), which disables the transmitter when inactive. Reset (RESET, pin 63), which puts the receiver in a sleep mode. The power down mode where, both RESET and RX_PE are used is the lowest possible power consumption mode for the receiver. Exiting this mode requires a maximum of 10s before the device is back at its operational mode for transmitters. Add 5ms more to be operational for receive mode. The contents of the Configuration Registers are not effected by any of the power down modes. No reconfiguration is required when returning to operational modes. Activation of RESET does corrupt learned values of AGC settings and
TABLE 2. POWER DOWN MODES MODE SLEEP RX_PE Inactive TX_PE Inactive RESET Active AT 44MHz 1mA DEVICE STATE Both transmit and receive functions disabled. Device in sleep mode. Control Interface is still active. Register values are maintained. Device will return to its active state within 10s plus settling time of AC coupling capacitors (about 5ms). Both transmit and receive operations disabled. Device will resume its operational state within 1s of RX_PE or TX_PE going active. Receiver operations disabled. Receiver will return in its operational state within 1s of RX_PE going active. Transmitter operations disabled. Transmitter will return to its operational state within 2 MCLKs of TX_PE going active. All inputs at VCC or GND.
STANDBY TX RX NO CLOCK
Inactive Inactive Active
Inactive Active Inactive
Inactive Inactive Inactive Active
1.5mA 10mA 100mA 300A
ICC Standby
9
HFA3861
TABLE 3. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz DATA MODULATION DBPSK DQPSK CCK CCK A/D SAMPLE CLOCK (MHz) 22 22 22 22 TX SETUP CR 5 BITS 1, 0 00 01 10 11 RX SIGNAL CR 63 BITS 7, 6 00 01 10 11 DATA RATE (Mbps) 1 2 5.5 11 SYMBOL RATE (MSPS) 1 1 1.375 1.375
802.11 DSSS BPSK 1Mbps BARKER DATA
802.11 DSSS QPSK 2Mbps BARKER
5.5Mbps CCK COMPLEX SPREAD FUNCTIONS
11Mbps CCK COMPLEX SPREAD FUNCTIONS
1 BIT ENCODED TO ONE OF 2 CODE WORDS (TRUE-INVERSE)
2 BITS ENCODED TO ONE OF 4 CODE WORDS
4 BITS ENCODED TO ONE OF 16 COMPLEX CCK CODE WORDS
8 BITS ENCODED TO ONE OF 256 COMPLEX CCK CODE WORDS
IOUT QOUT 11 CHIPS CHIP RATE SYMBOL RATE 11 MC/S 1 MS/S 11 CHIPS 11 MC/S 1 MS/S 8 CHIPS 11 MC/S 1.375 MS/S 8 CHIPS 11 MC/S 1.375 MS/S
I vs Q
FIGURE 7. MODULATION MODES
For the 1 and 2Mbps modes, the transmitter accepts data from the external source, scrambles it, differentially encodes it as either DBPSK or DQPSK, and spreads it with the BPSK PN sequence. The baseband digital signals are then output to the external IF modulator. For the CCK modes, the transmitter inputs the data and partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps, it uses two of those bits to select one of 4 complex spread sequences from a table of CCK sequences and then QPSK modulates that symbol with the remaining 2 bits. Thus, there are 4 possible spread sequences to send at four possible carrier phases, but only one is sent. This sequence is then modulated on the I and Q outputs. The initial phase reference for the data portion of the packet is the phase of the last bit of the header. At 11Mbps, one byte is used as above where 6 bits are used to select one of 64 spread sequences for a symbol and the other 2 are used to QPSK modulate that symbol. Thus, the total possible number of
combinations of sequence and carrier phases is 256. Of these only one is sent. The bit rate Table 3 shows examples of the bit rates and the symbol rates and Figure 7 shows the modulation schemes. The modulator is completely independent from the demodulator, allowing the PRISM baseband processor to be used in full duplex operation.
Header/Packet Description
The HFA3861 is designed to handle packetized Direct Sequence Spread Spectrum (DSSS) data transmissions. The HFA3861 generates its own preamble and header information. It uses two packet preamble and header configurations. The first is backwards compatible with the existing IEEE 802.11-1997 1 and 2Mbps modes and the second is the optional shortened mode which maximizes throughput at the expense of compatibility with legacy equipment.
10
HFA3861
In the long preamble mode, the device uses a synchronization preamble of 128 symbols along with a header that includes four fields. The preamble is all 1's (before entering the scrambler) plus a start frame delimiter (SFD). The actual transmitted pattern of the preamble is randomized by the scrambler. The preamble is always transmitted as a DBPSK waveform (1Mbps). The duration of the long preamble and header is 192s. In the short preamble mode, the modem uses a synchronization field of 56 zero symbols along with an SFD transmitted at 1Mbps. The short header is transmitted at 2Mbps. The synchronization preamble is all 0's to distinguish it from the long header mode and the short preamble SFD is the time reverse of the long preamble SFD. The duration of the short preamble and header is 96s. Start Frame Delimiter (SFD) Field (16 Bits) - This field is used to establish the link frame timing. The HFA3861 will not declare a valid data packet, even if it PN acquires, unless it detects the SFD. The HFA3861 receiver is programmed to time out searching for the SFD via CR 10 BITS 4 and 5. The timer starts counting the moment that initial PN synchronization has been established on the preamble. The four fields for the header shown in Figure 8 are: Signal Field (8 Bits) - This field indicates what data rate the data packet that follows the header will be. The HFA3861 receiver looks at the signal field to determine whether it needs to switch from DBPSK demodulation into DQPSK, or CCK demodulation at the end of the preamble and header fields. Service Field (8 Bits) - The MSB of this field is used to indicate the correct length when the length field value is ambiguous at 11Mbps. See IEEE STD 802.11 for definition of the other bits. These bits are not used by the HFA3861. Length Field (16 Bits) - This field indicates the number of microseconds it will take to transmit the payload data (PSDU). The external controller (MAC) will check the length field in determining when it needs to de-assert RX_PE. CCITT - CRC 16 Field (16 Bits)- This field includes the 16-bit CCITT - CRC 16 calculation of the three header fields. This value is compared with the CCITT - CRC 16 code calculated at the receiver. The HFA3861 receiver will indicate a CCITT CRC 16 error via CR24 bit 2 and will lower MD_RDY and reset the receiver to the acquisition mode if there is an error. The CRC or cyclic Redundancy Check is a CCITT CRC-16 FCS (frame check sequence). It is the ones compliment of the remainder generated by the modulo 2 division of the protected bits by the polynomial: x16 + x12 + x5 + 1 The protected bits are processed in transmit order. All CRC calculations are made prior to data scrambling. A shift register with two taps is used for the calculation. It is preset to all ones and then the protected fields are shifted through the register. The output is then complemented and the residual shifted out MSB first. The following Configuration Registers (CR) are used to program the preamble/header functions, more programming details about these registers can be found in the Control Registers section of this document: CR 4 - Defines the preamble length minus the SFD in symbols. The 802.11 protocol requires a setting of 128d = 80h. CR 10 bits 4,5 - Define the length of time that the demodulator searches for the SFD before returning to acquisition. CR 5 bits 0,1 - These bits of the register set the Signal field to indicate what modulation is to be used for the data portion of the packet. CR 6 - The value to be used in the Service field. CR 7 and 8 - Defines the value of the transmit data length field. This value includes all symbols following the last header field symbol and is in microseconds required to transmit the data at the chosen data rate. The packet consists of the preamble, header and MAC protocol data unit (MPDU). The data is transmitted exactly as received from the control processor. Some dummy bits will be appended to the end of the packet to insure an orderly shutdown of the transmitter. This prevents spectrum splatter. At the end of a packet, the external controller is expected to de-assert the TX_PE line to shut the transmitter down.
PREAMBLE (SYNC) 128/56 BITS
SFD 16 BITS
SIGNAL FIELD 8 BITS
SERVICE FIELD 8 BITS
LENGTH FIELD 16 BITS
CRC16 16 BITS
PREAMBLE
HEADER
FIGURE 8. 802.11 PREAMBLE/HEADER
11
HFA3861 Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the scrambling algorithm specified in the IEEE 802.11 standard. This scrambler is used for the preamble, header, and data in all modes. The data scrambler is a self synchronizing circuit. It consist of a 7-bit shift register with feedback from specified taps of the register. Both transmitter and receiver use the same scrambling algorithm. The scrambler can be disabled by setting CR32 bit 2 to 1.
NOTE: Be advised that the IEEE 802.11 compliant scrambler in the HFA3861 has the property that it can lock up (stop scrambling) on random data followed by repetitive bit patterns. The probability of this happening is 1/128. The patterns that have been identified are all zeros, all ones, repeated 10s, repeated 1100s, and repeated 111000s. Any break in the repetitive pattern will restart the scrambler. To insure that this does not cause any problem, the CCK waveform uses a ping pong differential coding scheme that breaks up repetitive 0s patterns.
DBPSK modulated, and the data and/or header are modulated differently. The modulator can support date rates of 1, 2, 5.5 and 11Mbps. The programming details to set up the modulator are given at the introductory paragraph of this section. The HFA3861 utilizes Quadraphase (I/Q) modulation at baseband for all modulation modes. In the 1Mbps DBPSK mode, the I and Q Channels are connected together and driven with the output of the scrambler and differential encoder. The I and Q Channels are then both multiplied with the 11-bit Barker word at the spread rate. The I and Q signals go to the Quadrature upconverter (HFA3724) to be modulated onto a carrier. Thus, the spreading and data modulation are BPSK modulated onto the carrier. For the 2Mbps DQPSK mode, the serial data is formed into dibits or bit pairs in the differential encoder as detailed above. One of the bits from the differential encoder goes to the I Channel and the other to the Q Channel. The I and Q Channels are then both multiplied with the 11-bit Barker word at the spread rate. This forms QPSK modulation at the symbol rate with BPSK modulation at the spread rate.
Scrambling is done by a division using a prescribed polynomial as shown in Figure 9. A shift register holds the last quotient and the output is the exclusive-or of the data and the sum of taps in the shift register. The taps are programmable. The transmit scrambler seed is Hex 6C for the long preamble or 1B for the short preamble and can be set with CR36 or CR37.
SERIAL DATA IN XOR SERIAL DATA OUT Z-1 Z-2 Z-3 Z-4 XOR Z-5 Z-6 Z-7
CCK Modulation
The spreading code length is 8 and based on complementary codes. The chipping rate is 11Mchip/s and the symbol duration is exactly 8 complex chips long. The following formula is used to derive the CCK code words that are used for spreading both 5.5 and 11Mbps:
j ( 1 + 2 + 3 + 4 ) j ( 1 + 3 + 4 ) j ( 1 + 2 + 4 ) c = e , ,e ,e -e
j ( 1 + 4 )
FIGURE 9. SCRAMBLING PROCESS
For the 1Mbps DBPSK data rates and for the header in all rates, the data coder implements the desired DBPSK coding by differential encoding the serial data from the scrambler and driving both the I and Q output channels together. For the 2Mbps DQPSK data rate, the data coder implements the desired coding as shown in the DQPSK Data Encoder table. This coding scheme results from differential coding of dibits (2 bits). Vector rotation is counterclockwise although bits 6 and 7 of configuration register CR 1 can be used to reverse the rotation sense of the TX or RX signal if desired.
TABLE 4. DQPSK DATA ENCODER PHASE SHIFT 0 +90 +180 -90 DIBIT PATTERN (d0, d1) d0 IS FIRST IN TIME 00 01 11 10
,e
j ( 1 + 2 + 3 )
,e
j ( 1 + 3 )
, -e
j ( 1 + 2 )
,e
j 1

(LSB to MSB), where c is the code word. The terms: 1, 2, 3, and 4 are defined below for 5.5Mbps and 11Mbps. This formula creates 8 complex chips (LSB to MSB) that are transmitted LSB first. The coding is a form of the generalized Hadamard transform encoding where 1 is added to all code chips, 2 is added to all odd code chips, 3 is added to all odd pairs of code chips and 4 is added to all odd quads of code chips. The phases 1 modify the phase of all code chips of the sequence and are DQPSK encoded for 5.5 and 11Mbps. This will take the form of rotating the whole symbol by the appropriate amount relative to the phase of the preceding symbol. Note that the last chip of the symbol defined above is the chip that indicates the symbol's phase. For the 5.5Mbps CCK mode, the output of the scrambler is partitioned into nibbles. The first two bits are encoded as differential modulation in accordance with Table 5 . All odd numbered symbols of the short Header or MPDU are given
Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and CCK spread spectrum signals. The modulator is capable of automatically switching its rate where the preamble is
12
HFA3861
an extra 180 degree () rotation in addition to the standard DQPSK modulation as shown in the table. The symbols of the MPDU shall be numbered starting with "0" for the first symbol for the purposes of determining odd and even symbols. That is, the MPDU starts on an even numbered symbol. The last data dibits d2, and d3 CCK encode the basic symbol as specified in Table 6. This table is derived from the formula above by setting 2 = (d2*pi)+ pi/2, 3 = 0, and 4 = d3*pi. In the table d2 and d3 are in the order shown and the complex chips are shown LSB to MSB (left to right) with LSB transmitted first.
TABLE 5. DQPSK ENCODING TABLE EVEN SYMBOLS ODD SYMBOLS DIBIT PATTERN (d(0), d(1)) PHASE CHANGE PHASE CHANGE d(0) IS FIRST IN TIME (+j) (+j) 00 01 11 10 0
TX Power Control
The transmitter power can be controlled by the MAC via two registers. The first register, CR58, contains the results of power measurements digitized by the HFA3861. By comparing this measurement to what the MAC needs for transmit power, the MAC can determine whether to raise or lower the transmit power. It does this by writing the power level desired to register CR31.
Clear Channel Assessment (CCA) and Energy Detect (ED) Description
The clear channel assessment (CCA) circuit implements the carrier sense portion of a carrier sense multiple access (CSMA) networking scheme. The Clear Channel Assessment (CCA) monitors the environment to determine when it is feasible to transmit. The CCA circuit in the HFA3861 can be programmed to be a function of RSSI (energy detected on the channel), CS1, CS2, or both. The CCA output can be ignored, allowing transmissions independent of any channel conditions. The CCA in combination with the visibility of the various internal parameters (i.e., Energy Detection measurement results), can assist an external processor in executing algorithms that can adapt to the environment. These algorithms can increase network throughput by minimizing collisions and reducing transmissions liable to errors. There are three measures that can be used in the CCA assessment. The receive signal strength indication (RSSI) which indicates the energy at the antenna, CS1 and carrier sense (CS2). CS2 becomes active only when a spread signal with the proper PN code has been detected, and the peak correlation amplitude exceeds a set threshold, so it may not be adequate in itself. CS1 becomes active anytime the AGC portion of the circuit becomes unlocked, which is likely at the onset of a signal that is strong enough to support 11Mbps, but may not occur with the onset of a signal that is only strong enough to support 1 or 2MBps. CS1 stays active until the AGC locks and a CS2 assessment is done, if CS2 is false, then CS1 is cleared, which deasserts CCA. If CS2 is true, then tracking is begun, and CCA continues to show the channel busy. CS1 may occur at any time during acquisition as the AGC state machine runs asynchronously with respect to slot times. A CS2 evaluation occurs whenever the AGC has remained locked for the entire data ingest period, when this happens, CS2 is updated between 8 and 9s into the 10s dwell. If CS1 is not active, two consecutive CS2's are required to advance the part to tracking. The state of CCA is not guaranteed from the time RX_PE goes high until the first CCA assessment is made. At the end of a packet, after RXPE has been deasserted, the state of CCA is also not guaranteed.
3/2 (-/2) 0
/2
3/2 (-/2)
/2
TABLE 6. 5.5Mbps CCK ENCODING TABLE d2, d3 00 : 01 : 10 : 11 : 1j -1j -1j 1j 1 -1 1 -1 1j -1j -1j 1j -1 1 -1 1 1j 1j -1j -1j 1 1 1 1 -1j -1j 1j 1j 1 1 1 1
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted per symbol. The first dibit (d0, d1) encodes 1 based on DQPSK. The DQPSK encoder is specified in Table 6 above. The phase change for 1 is relative to the phase 1 of the preceding symbol. In the case of rate change, the phase change for 1 is relative to the phase 1 of the preceding CCK symbol. All odd numbered symbols of the MPDU are given an extra 180 degree () rotation in accordance with the DQPSK modulation as shown in Table 7. Symbol numbering starts with "0" for the first symbol of the MPDU. The data dibits: (d2, d3), (d4, d5), (d6, d7) encode 2, 3, and 4 respectively based on QPSK as specified in Table 7. Note that this table is binary, not Grey, coded.
TABLE 7. QPSK ENCODING TABLE DIBIT PATTERN (d(i), d(i+1)) d(i) IS FIRST IN TIME 00 01 10 11 PHASE 0
/2
3/2 (-/2)
13
HFA3861
The receive signal strength indication (RSSI) measurement is derived from the state of the AGC circuit and the output of the AGC detector. The RSSI value can be compared to a programmable threshold. The result of this compare (ED) will update asynchronously with respect to slot boundaries. This threshold is normally set to between -70 and -80dBm. A MAC controlled calibration procedure can be used to optimize this threshold. The Configuration registers effecting the CCA algorithm operation are summarized below (more programming details on these registers can be found under the Control Registers section of this document). The CCA output from pin 60 of the device can be defined as active high or active low through CR 1 (bit 2). CR9(6:5) allow CCA to be programmed to be a function of ED only, the logical operation of (CS1 OR CS2), the logical function of (ED AND (CS1 OR CS2), or just CS2. CR11(3) lets the user select from sampled CCA mode, which means CCA will not glitch, is updated once per symbol and is valid for reading at 19.8s. In non-sampled mode, CCA may change at anytime, potentially several times per slot, as ED and CS1 operate asynchronously to slot times. In a typical system CCA will be monitored to determine when the channel is clear. Once the channel is detected busy, CCA should be checked periodically to determine if the channel becomes clear. CCA can be programmed to be stable to allow asynchronous sampling or even falling edge detection of CCA. Once MD_RDY goes active, CCA is then ignored for the remainder of the message. Failure to monitor CCA until MD_RDY goes active (or use of a time-out circuit) could result in a stalled system as it is possible for the channel to be busy and then become clear without an MD_RDY occurring. lock window, the BBP declares AGC lock and stops adjusting for the duration of the packet. We look for this locked state following an unlocked state as one indication that a received signal is on the antenna. This starts the receive process of looking for PN correlation. Once PN correlation and AGC lock are found, the processor begins acquisition. For large signals, the power level in the RF stage output is also monitored and if it is large, the LNA stage is shut down. This removes 30dB of gain from the receive chain which is compensated for by replacing 30dB of gain in the IF AGC stage. There is some hysteresis in this operation. This improves the receiver dynamic range.
Demodulator Description
The receiver portion of the baseband processor, performs A/D conversion and demodulation of the spread spectrum signal. It correlates the PN spread symbols, then demodulates the DBPSK, DQPSK, or CCK symbols. The demodulator includes a frequency tracking loop that tracks and removes the carrier frequency offset. In addition it tracks the symbol timing, and differentially decodes (where appropriate) and descrambles the data. The data is output through the RX Port to the external processor. The PRISM baseband processor, HFA3861 uses differential demodulation for the initial acquisition portion of the message processing and then switches to coherent demodulation for the MPDU demodulation. The HFA3861 is designed to achieve rapid settling of the carrier tracking loop during acquisition. Rapid phase fluctuations are handled with a relatively wide loop bandwidth. Coherent processing improves the BER performance margin as opposed to differentially coherent processing for the CCK data rates. The baseband processor uses time invariant correlation to strip the PN spreading and phase processing to demodulate the resulting signals in the header and DBPSK/DQPSK demodulation modes. These operations are illustrated in Figure 13 which is an overall block diagram of the receiver processor. In processing the DBPSK header, input samples from the I and Q A/D converters are correlated to remove the spreading sequence. The peak position of the correlation pulse is used to determine the symbol timing. The sample stream is decimated to the symbol rate and corrected for frequency offset prior to PSK demodulation. Phase errors from the demodulator are fed to the NCO through a lead/lag filter to maintain phase lock. The demodulated data is differentially decoded and descrambled before being sent to the header detection section. In the 1Mbps DBPSK mode, data demodulation is performed the same as in header processing. In the 2Mbps DQPSK mode, the demodulator demodulates two bits per symbol
AGC Description
The AGC system consists of the 3 chips handling the receive signal, the RF to IF downconverter, the IF to baseband converter, and the baseband processor. The AGC loop is digitally controlled by the BBP. Basically it operates as follows: Initially, the radio is set for high gain. The percent of time that the A/D converters in the baseband processor are saturated versus not saturated is monitored along with signal amplitude and the gain is adjusted down until the amplitude is what will optimize the demodulator's performance. If the amount of saturation is great, the initial gain adjust steps are large. If the signal overload is small, they are less. If the signal level then varies more than a preset amount, the AGC is declared unlocked and the gain again allowed to readjust. When the gain is right and the A/Ds' outputs are within the
14
HFA3861
and differentially decodes these bit pairs. The bits are then serialized and descrambled prior to being sent to the output. In the CCK modes, the receiver uses a complex multiplier to remove carrier frequency offsets and a bank of correlators to detect the modulation. A biggest picker finds the largest correlation in the I and Q Channels and determines the sign of those correlations. For this to happen, the demodulator must know absolute phase which is determined by referencing the data to the last bit of the header. Each symbol demodulated determines 1 or 2 nibbles of data. This is then serialized and descrambled before being passed to the output. Chip tracking in the CCK modes is chip decision directed. Carrier tracking is via a lead/lag filter using a digital Costas phase detector. case time line example assumes that the signal arrives part way into the first dwell such as to just barely catch detection. The signal and the scanning process are asynchronous and the signal could start anywhere. In this timeline, it is assumed that the signal is present in the first 10s dwell, but was missed due to power amplifier ramp up. Meanwhile signal quality and signal frequency measurements are made simultaneous with symbol timing measurements. A CS1 followed by CS2 active, or two consecutive CS2's will cause the part to exit the acquisition phase and enter the tracking phase. CR10(7) can be used to restrict the part to using only consecutive CS2's as the requirement to enter tracking. Prior to initial acquisition the NCO was inactive and DPSK demodulation processing was used. Carrier phase measurement are done on a symbol by symbol basis afterward and coherent DPSK demodulation is in effect. After a brief setup time as illustrated on the timeline of, the signal begins to emerge from the demodulator. It takes 7 more symbols to seed the descrambler before valid data is available. This occurs in time for the SFD to be received. At this time the demodulator is tracking and in the coherent PSK demodulation mode it will no longer acquire signals.
Acquisition Description
A projected worst case time line for the acquisition of a signal with a short preamble and header is shown. The synchronization part of the preamble is 56 symbols long followed by a 16-bit SFD. The receiver must monitor the antenna to determine if a signal is present. The timeline is broken into 10s blocks (dwells) for the scanning process. This length of time is necessary to allow enough integration of the signal to make a good acquisition decision. This worst
TX POWER RAMP 56 SYMBOL SYNC 2 20 SYMBOLS AGC SETTLE AND LOCK AND INITIAL DETECTION 20 SYMBOLS VERIFY AND CIR/FREQUENCY ESTIMATION AND CMF/NCO JAMMING 7 SYM SFD 16 SYMBOLS
SEED DESCRAMBLER START SFD DETECTION
SFD DET START DATA
FIGURE 10. ACQUISITION TIMELINE
15
HFA3861
VDD (ANALOG) (12, 17, 22, 31) GND (ANALOG) (9, 15, 20, 25, 28) VDD (DIGITAL) (2, 8, 37, 41, 57) GND (DIGITAL) (1, 7, 36, 43, 56)
IREF (21) OUTPUT MUX
(52) RXCLK (60) CCA
VREF (16) TEST CONTROL 6-BIT ADC TX AGC CONTROL TX_IF_AGC (35) SPARE (39) ANTSEL (40) REGISTER TRANSMIT FILTER 6-BIT DAC
TXI (23, 24) DAC
TX_AGC_IN (18)
OUTPUT MUX
TXQ (29, 30) DAC
PREAMBLE/HEADER CRC-16 GENERATOR
TRANSMIT PORT
(59) TX_RDY (55) TXCLK MODULATOR, BARKER/CCK TX_DATA SCRAMBLER PROCESSOR INTERFACE (58) TXD
SERIAL CONTROL PORT
TX STATE CONTROL
(3) SD (4) SCLK (64) SDI (5) R/W (6) CS
TIMING GENERATOR MCLK
TEST PORT
(62) TX_PE
TEST 0
TEST 1
TEST 2
TEST 3
TEST 4
TEST 5
TEST 6
FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
PN Correlators Description
There are two types of correlators in the HFA3861 baseband processor. The first is a parallel matched correlator that correlates for the Barker sequence used in preamble, header, and PSK data modes. This PN correlator is designed to handle BPSK spreading with carrier offsets up to 50ppm and 11 chips per symbol. Since the spreading is BPSK, the correlator is implemented with two real correlators, one for the I and one for the Q Channel. The same Barker sequence is always used for both I and Q correlators. These correlators are time invariant matched filters otherwise known as parallel correlators. They use one sample per chip for correlation although two samples per chip are processed. The correlator despreads the samples from the chip rate back to the original data rate giving 10.4dB processing gain for 11 chips per bit. While despreading the desired signal, the correlator spreads the energy of any non correlating interfering signal. The second form of correlator is the correlator function used for detection of the CCK modulation. For the CCK modes,
16
TEST 7
(42) MCLK
(44) (45) (46) (47) (48) (49) (50) (51)
HFA3861
the correlation function uses a Fast Walsh Transform to correlate the 4 or 64 code possibilities followed by a biggest picker. The biggest picker finds the biggest of 4 or 64 correlator outputs depending on the rate. This is translated into 2 or 6 bits. The detected output is then processed through the differential decoder to demodulate the last two bits of the symbol.
TABLE 8. DQPSK DATA DECODER PHASE SHIFT 0 +90 +180 -90 DIBIT PATTERN (D0, D1) D0 IS FIRST IN TIME 00 01 11 10
Data Demodulation and Tracking Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks tracked by the symbol timing loop (bit sync) as shown in Figure 12. The frequency and phase of the signal is corrected using the NCO that is driven by the phase locked loop. Demodulation of the DBPSK data in the early stages of acquisition is done by differential detection. Once phase locked loop tracking of the carrier is established, coherent demodulation is enabled for better performance. Averaging the phase errors over 10 symbols gives the necessary frequency information for proper NCO operation. Configuration Register 15 sets the search timer for the SFD. This register sets this time-out length in symbols for the receiver. If the time out is reached, and no SFD is found, the receiver resets to the acquisition mode. The suggested value is the number of preamble symbols plus 16. If different transmit preamble lengths are used by various transmitters in a network, the longest value should be used for the receiver settings.
The data scrambler and de-scrambler are self synchronizing circuits. They consist of a 7-bit shift register with feedback of some of the taps of the register. The scrambler is designed to insure smearing of the discrete spectrum lines produced by the PN code. One thing to keep in mind is that both the differential decoding and the descrambling cause error extension or burst errors. This is due to two properties of the processing. First, the differential decoding process causes errors to occur on pairs of symbols. When a symbol's phase is in error, the next symbol will also be decoded wrong since the data is encoded in the change in phase from one symbol to the next. Thus, two errors are made on two successive symbols. Therefore up to 4 bits may be wrong although on the average only 2 are. In QPSK mode, these may occur next to one another or separated by up to 2 bits. In the CCK mode, when a symbol decision error is made, up to 6 bits may be in error although on average only 3 bits will be in error. Secondly, when the bits are processed by the descrambler, these errors are further extended. The descrambler is a 7-bit shift register with two taps exclusive or'ed with the bit stream. Thus, each error is extended by a factor of three. Multiple errors can be spaced the same as the tap spacing, so they can be canceled in the descrambler. In this case, two wrongs do make a right. Given all that, if a single error is made the whole packet is discarded anyway, so the error extension property has no effect on the packet error rate. Descrambling is self synchronizing and is done by a polynomial division using a prescribed polynomial. A shift register holds the last quotient and the output is the exclusiveor of the data and the sum of taps in the shift register.
Data Decoder and Descrambler Description
The data decoder that implements the desired DQPSK coding/decoding as shown in Table 8. The data is formed into pairs of bits called dibits. The left bit of the pair is the first in time. This coding scheme results from differential coding of the dibits. Vector rotation is counterclockwise for a positive phase shift, but can be reversed with bit 7 or 6 of CR 1. For DBPSK, the decoding is simple differential decoding.
SAMPLES AT 2X CHIP RATE
CORRELATION PEAK
CORRELATION TIME
T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PN SEQUENCE WITH THE RECEIVED SIGNAL
T0 + 1 SYMBOL CORRELATOR OUTPUT REPEATS
T0 + 2 SYMBOLS EARLY ON-TIME LATE
FIGURE 12. CORRELATION PROCESS
17
HFA3861
VDD (ANALOG) (12, 17, 22, 31) GND (ANALOG) (9, 15, 20, 25, 28) VDD (DIGITAL) (2, 8, 37, 41, 57) GND (DIGITAL) (1, 7, 36, 43, 56)
RX_IF_DET (19) RX_IF_AGC (34) RX-RF-AGC (38) 6-BIT DAC AGC CONTROL CLEAR CHANNEL ASSESSMENT/ SIGNAL QUALITY CMF TRAINING
(60) CCA
CORRELATOR BARKER
8 PEAK EXTRACT. 8
BIT SYNC
RXI (10, 11)
6-BIT A/D
SAMPLE INTERPOLATOR, CHANNEL MATCHED FILTER
6
COMPLEX MULTIPLY
DPSK DEMOD
RXQ (13, 14)
6-BIT A/D
6
RX_DATA DESCRAMBLER SIN/COS ROM SYMBOL TRACKING PREAMBLE/HEADER CRC-16 DETECT RECEIVE PORT
(53) RXD (52) RXCLK
(54) MD_RDY
CHIP DE COVER
FAST WALSH TRANSFM
SYMBOL DECISION
NCO
LEAD /LAG FILTER (3) SD (4) SCLK (64) SDI (5) R/W (6) CS
ANTSEL (40)
TEST CONTROL
MUX
ANTENNA SWITCH CONTROL
RECEIVE STATE MACHINE
6-BIT DAC
SERIAL CONTROL PORT
TXI (23, 24)
MUX
6-BIT DAC TEST PORT
TXQ (29, 30)
TIMING GENERATOR MCLK
TEST 0
TEST 1
TEST 2
TEST 3
TEST 4
TEST 5
TEST 6
FIGURE 13. DSSS BASEBAND PROCESSOR, RECEIVE SECTION
18
TEST 7
(63) RESET
(61) RX_PE
(42) MCLK
(44)
(45)
(46) (47) (48) (49) (50) (51)
HFA3861 Data Demodulation in the CCK Modes
In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two highest data rates. It is slaved to the low rate processor which it depends on for acquisition of initial timing and phase tracking information. The low rate section acquires the signal, locks up symbol and carrier tracking loops, and determines the data rate to be used for the MPDU data. The demodulator for the CCK modes takes over when the preamble and header have been acquired and processed. On the last bit of the header, the phase of the signal is captured and used as a phase reference for the high rate differential demodulator. Control of the demodulator is then passed to the high rate section. The signal from the A/D converters is carrier frequency and phase corrected by a complex multiplier (mixer) that multiplies the received signal with the output of the Numerically Controlled Oscillator (NCO) and SIN/COS look up table. This removes the frequency offset and aligns the I and Q Channels properly for the correlators. The sample rate is decimated to 11MSPS for the correlators after the complex multiplier since the data is now synchronous in time. The Fast Walsh transform correlation section processes the I and Q channel information. The demodulator knows the symbol timing, so the correlation is batch processed over each symbol. The correlation outputs from the correlator are compared to each other in a biggest picker and the chosen one determines 6 bits of the symbol. The QPSK phase of the chosen one determines two more bits for a total of 8 bits per symbol. Six bits come from which of the 64 correlators had the largest output and the last two are determined from the QPSK differential demod of that output. In the 5.5Mbps mode, only 4 of the correlator outputs are monitored. This demodulates 2 bits for which of 4 correlators had the largest output and 2 more for the QPSK demodulation of that output for a total of 4 bits per symbol. The symbol clock is tracked by a sample interpolator that can adjust the sample timing forwards and backwards by 72 increments of 1/8th chip. This approach means that the HFA3861 can only track an offset in timing for a finite interval before the limits of the interpolator are reached. Thus, continuous demodulation is not possible. Carrier tracking is performed in a four phase Costas loop. This forms the error term that is integrated in the lead/lag filter for the NCO, closing the loop.
Demodulator Performance
This section indicates the typical performance measures for a radio design. The performance data below should be used as a guide. In general, the actual performance depends on the application, interference environment, RF/IF implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and energy efficient in packet mode communications. The demodulator uses coherent processing for data demodulation. The figures below show the performance of the baseband processor when used in conjunction with the HFA3783 IF and the PRISM recommended IF filters. Off the shelf test equipment are used for the RF processing. The curves should be used as a guide to assess performance in a complete implementation. Factors for carrier phase noise, multipath, and other degradations will need to be considered on an implementation by implementation basis in order to predict the overall performance of each individual system. Figure 14 shows the curves for theoretical DBPSK/DQPSK demodulation with coherent demodulation and descrambling as well as the PRISM performance measured for DBPSK and DQPSK. The theoretical performance for DBPSK and DQPSK are the same as shown on the diagram. Figure 15 shows the theoretical and actual performance of the CCK modes. The losses in both figures include RF and IF radio losses; they do not reflect the HFA3861 losses alone. The HFA3861 baseband processing losses from theoretical are, by themselves, a small percentage of the overall loss. The PRISM demodulator performs with an implementation loss of less than 3dB from theoretical in a AWGN environment with low phase noise local oscillators. For the 1 and 2Mbps modes, the observed errors occurred in groups of 4 and 6 errors. This is because of the error extension properties of differential decoding and descrambling. For the 5.5 and 11Mbps modes, the errors occur in symbols of 4 or 8 bits each and are further extended by the descrambling. Therefore the error patterns are less well defined.
Tracking
Carrier tracking is performed on the de-rotated signal samples from the complex multiplier. These are alternately routed into two streams. The END chip samples are the same as those used for the correlators. The MID chip samples should lie on the chip transitions when the tracking is perfect. A chip phase error is generated if the END sign bits bracketing the MID samples are different. The sign of the error is determined by the sign of the END sample after the MID sample. Tracking is only measured when there is a chip transition. Note that this tracking is dependent on a positive SNR in the chip rate bandwidth.
19
HFA3861
Eb/N0 7 8 9 10 11 12 1.E+00 1.E-01 1.E-02 BER 2.0 1.E-03 BER 1.0 BER BER THY 1, 2 1.E-04 1.E-05 1.E-06 1.E-06 1.E-07 1.E-07 1.E-08 1.E-08 1.E-09 1.E-03 1.E-04 1.E-05 THY 11 BER 5.5 THY 5.5 5 1.E+00 1.E-01 1.E-02 BER 11 6 7 8 Eb/N0 9 10
11
12
13
14
FIGURE 14. BER vs Eb/N0 PERFORMANCE FOR PSK MODES
FIGURE 15. BER vs Eb/N0 PERFORMANCE FOR CCK MODES
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data clock offsets of up to 25ppm for each end of the link (TX and RX). This effects both the acquisition and the tracking performance of the demodulator. The budget for clock offset error is 0.75dB at 50ppm. No appreciable degradation was seen for operation in AWGN at 50ppm.
Carrier Offset Frequency Performance
The correlators used for acquisition for all modes and for demodulation in the 1 and 2Mbps modes are time invariant matched filter correlators otherwise known as parallel correlators. They use two samples per chip and are tapped at every other shift register stage. Their performance with carrier frequency offsets is determined by the phase roll rate due to the offset. For an offset of +50ppm (combined for both TX and RX) will cause the carrier to phase roll 22.5 degrees over the length of the correlator. This causes a loss of 0.22dB in correlation magnitude which translates directly to Eb/N0 performance loss. In the PRISM chip design, the correlator is not included in the carrier phase locked loop correction during acquisition.
20
HFA3861 A Default Register Configuration
The registers in the HFA3861 are addressed with 7-bit numbers where the lower 1 bit of an 8-bit hexadecimal address is left as unused. This results in the addresses being in increments of 2 as shown in the table below. Table 9 shows the register values for a default 802.11 configuration with various rate configurations. The data is transmitted as either DBPSK, DQPSK, or CCK depending on the configuration chosen. It is recommended that you start with the simplest configuration (DBPSK) for initial test and verification of the device and/or the radio design. The user can later modify the CR contents to reflect the system and the required performance of each specific application.
TABLE 9. CONTROL REGISTER VALUES CONFIGURATION REGISTER CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 Part/Version Code I/O Polarity I Cover Code Q Cover Code TX Preamble Length TX Signal Field TX Service Field TX Length Field, High TX Length Field, Low TX Configure RX Configure RX/TX Configure A/D Test Modes 1 A/D Test Modes 2 A/D Test Modes 3 AGC GainClip AGC LowerSatCount AGC TimerCount AGC HiSat AGC LockinLevel AGC LockWindow AGC Threshold AGC Lookup Table Addr and Control AGC Lookup Table Data AGC LoopGain AGC RX_IF AGC Test Modes AGC RX_RF Threshold AGC Low SatAtten AGC Min SigAtten Carrier Sense 2 Manual TX Power Control Test Modes 1 Test Modes 2 Test Bus Address CMF Coefficient Control Scrambler Seed, Long Preamble Option Scrambler Seed, Short Preamble Option ED Threshold NAME TYPE R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REGISTER ADDRESS HEX 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 1/2/5.5/11Mbps 10 00 48 48 80 0b As Required As Required As Required 00 38 13 04 00 00 54 63 20 68 04 0A 12 (Note 3) (Note 3) 10 20 00 18 66 68 24 A0 00 00 00 18 6C 1B 7f
21
HFA3861
TABLE 9. CONTROL REGISTER VALUES (Continued) CONFIGURATION REGISTER CR39 CR40 CR41 CR42 CR43 CR44 CR45 CR46 CR47 CR48 CR49 CR50 CR51 CR52 CR53 CR54 CR55 CR56 CR57 CR58 CR59 CR60 CR61 CR62 CR63 NOTE: 3. This register is written, then the data is loaded into register 23 as per the following table. AGC REGISTER SETTINGS CR22 DECIMAL 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 CR23 HEX 00 04 08 0C 10 13 17 1B 22 26 29 2B 31 34 36 38 AGC REGISTER SETTINGS (Continued) CR22 DECIMAL 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CR23 HEX 3A 3E 43 49 51 54 58 5C 60 64 68 6C 70 74 78 7C CMF Gain Threshold Reserved, Must be Set to 00h Reserved, Must be Set to 00h Reserved, Must be Set to 00h Reserved, Must be Set to 00h Reserved, Must be Set to 00h Reserved, Must be Set to 00h Reserved, Must be Set to 00h Reserved, Must be Set to 00h SQ1 Reserved, Must be Set to 00h Test Bus Read Signal Quality Measure Based on Carrier Tracking Received Signal Field Received Service Field Received Length Field, High Received Length Field, Low Calculated CRC on Received Header, High Calculated CRC on Received Header, Low TX Power Measurement RX Mean Power RX_IF AGC RX Status Reg RSSI RX Status Reg NAME TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R REGISTER ADDRESS HEX 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 7A 7C 7E 1/2/5.5/11Mbps 2D 00 00 00 00 00 00 00 00 1A 00 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
22
HFA3861 Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Bit 3:0 Part Code 1 = HFA3861 series Version Code 0 = 3861 base Version CONFIGURATION REGISTER 1 ADDRESS (02h) R/W I/O POLARITY This register is used to define the phase of clocks and other interface signals. 00h is normal setting. Bit 7 This control bit selects the phase of the receive carrier rotation sense Logic 1 = Inverted rotation (CW), Invert Q in Logic 0 = normal rotation (CCW) This control bit selects the phase of the transmit carrier rotation sense Logic 1 = Inverted rotation (CW), Invert Q out. Logic 0 = normal rotation (CCW) This control bit selects the phase of the transmit output clock (TXCLK) pin Logic 1 = Inverted TXCLK Logic 0 = NON-Inverted TXCLK This control bit selects the active level of the Transmit Ready (TX_RDY) output which is an output pin at the test port, pin Logic 1 = TX_RDY Active 0 Logic 0 = TX_RDY Active 1 This control bit selects the active level of the transmit enable (TX_PE) input pin Logic 1 = TX_PE Active 0 Logic 0 = TX_PE Active 1 This control bit selects the active level of the Clear Channel Assessment (CCA) output pin. Logic 1 = CCA Active 1 Logic 0 = CCA Active 0 This control bit selects the active level of the MD_RDY output pin. Logic 1 = MD_RDY is Active 0 Logic 0 = MD_RDY is Active 1 This controls the phase of the RX_CLK output Logic 1 = Invert Clk Logic 0 = Non-Inverted Clk
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIGURATION REGISTER 2 ADDRESS (04h) R/W I COVER CODE Write to control, Read to verify control, setup while TX_PE and RX_PE are low Bits 0 - 7 I cover code, nominally 48h
CONFIGURATION REGISTER 3 ADDRESS (06h) R/W Q COVER CODE Bits 0 - 7 Q cover code, nominally 48h CONFIGURATION REGISTER 4 ADDRESS (08h) R/W TX PREAMBLE LENGTH Bits 0 - 7 This register contains the count for the Preamble length counter. Setup while TX_PE is low. For IEEE 802.11 use 80h. For other than IEEE 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value is 56d = 38h. These suggested values include a 2 symbol TX power amplifier ramp up. If you program 128 you get 130.
23
HFA3861
CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD Bits 7:4 Bits 3 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Select preamble mode 0 = Normal, long preamble interoperable with 1 and 2Mbps legacy equipment 1= short preamble and header mode (optional in 802.11) reserved, must be set to 0 TX data Rate. Must be set at least 2s before needed in TX frame. This selects TX signal field code from the registers above. 00 = DBPSK - 11 chip sequence (1Mbps) 01 = DQPSK - 11 chip sequence (2Mbps) 10 = CCK - 8 chip sequence (5.5Mbps) 11 = CCK - 8 chip sequence (11Mbps) CONFIGURATION REGISTER 6 ADDRESS (0Ch) R/W TX SERVICE FIELD Bits 7:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 7 may be employed by the MAC in 802.11 situations to resolve an ambiguity in the length field when in the 11Mbps mode. CONFIGURATION REGISTER 7 ADDRESS (0Eh) R/W TX LENGTH FIELD (HIGH) Bits 7:0 This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte combined with the lower byte indicates the number of microseconds the data packet will take. CONFIGURATION REGISTER 8 ADDRESS (10h) R/W TX LENGTH FIELD (LOW) Bits 7:0 This 8-bit register contains the lower byte (bits 0-7) of the transmit Length Field described in the Header. This byte combined with the higher byte indicates the number of microseconds the data packet will take. CONFIGURATION REGISTER 9 ADDRESS (12h) R/W TX CONFIGURE Bit 7 Bits 6:5 Unused CCA mode 00 - CCA is based only on ED 01 - CCA is based on (CS1 OR CS2) 10 - CCA is based on (ED AND (CS1 OR CS2)) 11 - CCA is based on CS2 only Reserved, must be set to 0 Reserved, must be set to 0 TX Antenna Selection 0x = set antenna select pin low during transmit 1x = set antenna select pin high during transmit R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE Bit 7 Acquisition mode 0 - Use CS1 followed by CS2, or two consecutive CS2s 1 - Use only consecutive CS2s R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. SFD Time-out values 00 = 56s 01 = 64s 10 = 128s 11 = 144s MD_RDY control 0 = After CRC16 1 = After SFD R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. antenna choice for Receive 0 = Antenna select pin low 1 = Antenna select pin high R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 2 Bits 1:0
Bit 4 Bit 3 Bit 2:1
Bit 0
Bit 6 Bits 5:4
Bit 3
Bit 2 Bit 1
Bit 0
24
HFA3861
CONFIGURATION REGISTER 11 ADDRESS (16h) R/W RX-TX CONFIGURE Bit 7 Bit 6 reserved, must be set to 0 A/D input coupling 0 = DC 1 = AC (external bias network required) TX filter / CMF weight select 0 = US 1 = Japan Ping Pong Differential Encode enable 0 = normal Ping Pong Differential encoding 1 = standard differential encoding Sampled CCA mode 0 = normal CCA. CCA will immediately respond to changes in ED, CS1, and CS2 as configured 1 = Sampled CCA. CCA will update once per slot (20s), will be valid at 19.8s. Precursor value in CIR estimate set to 011 binary CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 Bit 7 All DAC and A/D clock source control 0 = normal 1 = SDI TX DAC clock 0 = enable 1 = disable RX DAC clock 0 = enable 1 = disable I DAC clock 0 = enable 1 = disable Q DAC clock 0 = enable 1 = disable RF A/D clock 0 = enable 1 = disable I A/D clock 0 = enable 1 = disable Q A/D clock 0 = enable 1 = disable CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2 Bit 7 Standby 1 = enable 0 = disable SLEEPTX 1 = enable 0 = disable SLEEP RX 1 = enable 0 = disable SLEEP IQ 1 = enable 0 = disable
Bit 5
Bit 4
Bit 3
Bits 2:0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
bit 0
Bit 6
Bit 5
Bit 4
25
HFA3861
CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2 (Continued) Bit 3 Analog TX Shut_down 1 = enable 0 = disable Analog RX Shut_down 1 = enable 0 = disable Analog Standby 1 = enable 0 = disable Enable manual control of mixed signal power down signals using bits 1:7 1 = enable 0 = disable, normal operation (devices controlled by RESET, TX_PE, RX_PE) CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3 Bit 7 Bits 6:4 DFS- select straight binary output of I/Q and RF A/D converters I/Q DAC input control. This DAC gives an analog look at various internal digital signals that are suitable for analog representation. 000 = normal (TX filter) 001 = down converter 010 = E/L integrator - upper 6 bits (Q) and AGC error (I) 011 = I/ Q A/D's 100 = Bigger picker output. Upper 6 bits of FWT_I winner and FWT_Q winner 101 = CMF weights - upper 6 bits of all 16 CMF weights are circularly shifted with full scale negative sync pulse interleaved between them 110 = TestBus pins (5:0) when configured as inputs, CR32(4), to both I and Q inputs 111 = Barker Correlator/ low rate samples - as selected by bit 7 CR32 Enable test bus into RX and TX DAC (if below bit is 0) 0 = normal 1 = enable Enable RF A/D into RX DAC 0 = normal 1 = enable VRbit1 VRbit0 CONFIGURATION REGISTER 15 ADDRESS (1Eh) R/W AGC CONTROL 1 Bit 7 Bits 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC gain clip (7 bit value, MSB unused) CONFIGURATION REGISTER 16 ADDRESS (20h) R/W AGC CONTROL 2 Bits 7:4 Bits 3:0 AGC mid Sat counts (0-15 range) AGC low Sat Count (0-15 range) CONFIGURATION REGISTER 17 ADDRESS (22h) R/W AGC CONTROL 4 Bits 7:6 Bit 5:0 Unused, set to 0 AGC timer count (number of clocks in AGC cycle, 0-63 range) CONFIGURATION REGISTER 18 ADDRESS (24h) R/W AGC CONTROL 5 Bits 7:4 Bits 3:0 AGC high sat attenuation (0-60) AGC (0-15 range)
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1 Bit 0
26
HFA3861
CONFIGURATION REGISTER 19 ADDRESS (26h) R/W AGC CONTROL 6 Bits 7:5 Bits 4:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC Lock-in level (0-7.5 range) CONFIGURATION REGISTER 20 ADDRESS (28h) R/W AGC CONTROL 7 Bits 7:5 Bit 4:0 R/W, But Not Used Internally AGC Lock Window (0-15.5 range) CONFIGURATION REGISTER 21 ADDRESS (2Ah) R/W AGC CONTROL 8 Bits 7,6 Bits 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC Threshold (0-31.5 range) CONFIGURATION REGISTER 22 ADDRESS (2Ch) R/W AGC CONTROL 9 Bits 7,6 Bits 5 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC Look up table read control bit 1 = Read 0 = write AGC lookup table address (32 address bits) CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC CONTROL 10 Bits 7 Bits 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC look up table data unsigned CONFIGURATION REGISTER 24 ADDRESS (30h) R/W AGC CONTROL 11 Bits 7 Bit 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC loop gain (0.xxxx - 1.0000 range) CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC CONTROL 12 Bits 7 Bits 6:0 AGC RX_RF, This input drives the RF RF control if AGC override Enable is set to 1 AGC RX_IF, This reg is input to RF IF DAC if AGC override Enable is set to 1 CONFIGURATION REGISTER 26 ADDRESS (34h) R/W AGC TEST MODES Bits 7:4 Bit 3 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC run on freeze- AGC keeps running after acquisition is complete, only signal is updated, no changes to IF or RF gain occur 0 = normal 1 = enabled AGC override Enable, if set, CR25 controls receiver gain in both RF and IF 0 = normal 1 = enabled AGC random I/Q allows random data on AGC 6 bit I/Q inputs if PN is enabled 0 = normal 1 = enabled AGC test math- always accumulates in gain adjust, always outputs mean power from log table. 0 = normal 1 = enabled
Bits 4:0
Bit 2
Bit 1
Bit 0
27
HFA3861
CONFIGURATION REGISTER ADDRESS 27 (36h) R/W AGC RF THRESHOLD Bits 7 Bit 6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. RXRF flag 0 = normal 1 = disables threshold AGC threshold (0-64 range) CONFIGURATION REGISTER ADDRESS 28 (38h) R/W AGC LOW SAT ATTENUATOR Bits 7:4 Bits 3:0 Mid sat attenuation (0-30 range) low sat attenuation (0-15 range) CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC MINIMUM SIGNAL ATTENUATION Bits 7:0 AGC minimum signal attenuation (0-64 range), 2's compliment CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR Bits 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Carrier Sense 2 scale factor (0-4 range) (000000 - 100000) CONFIGURATION REGISTER 31 ADDRESS (3Eh) MANUAL TX POWER CONTROL Bits 7:1 Bit 0 7 bits to DAC input, -64 to 63 range unused CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1 Bit 7 Selection bit for DAC input test mode 7 0 = Barker 1 = Low rate I/Q samples force high rate mode 0 = normal 1 = force high rate mode TX 44 clock enable 0 = Normal 1 = enabled Tristate test bus and enable inputs 0 = Normal 1 = enable inputs on test bus Disable spread sequence for 1 and 2Mbps 0 = Normal 1 = disabled Disable scrambler 0 = normal scrambler operation 1 = scrambler disabled (taps set to 0) PN generator enable (RX 44MHz clock) 0 = not enabled 1 = enabled PN generator enable (RX 22MHz clock) 0 = not enabled 1 = enabled
Bits 5:0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
28
HFA3861
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TE4ST MODES 2 Bits 7:4 Bit 3 Unused, set to 0 disable time adjust 0 = normal 1 = disabled Internal digital loop back mode (SDI pin becomes LOCK input to acquisition block) 0 = normal chip operation loop back disabled 1 = loop back enabled, A/D and D/A converters bypassed, chip will not respond to external signals enable PN to lower test bus address (2-0) 0 = normal 1 = PN to test bus address enable PN to upper test bus address (7-3) 0 = normal 1 = PN to test bus address CONFIGURATION REGISTER ADDRESS 34 (44h) R/W TEST BUS ADDRESS Bits 7:0 address bits for various tests. See Tech Brief #TBD for a description of the factory test modes CONFIGURATION REGISTER ADDRESS 35 (46h) R/W CMF COEFFICIENT CONTROL THRESHOLD Bit 7 Bit 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. 00h will force use of calculated weights 07h will force use of defaults CONFIGURATION REGISTER ADDRESS 36 (48h) R/W SCRAMBLER SEED LONG PREAMBLE Bit 7 Bit 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. scrambler seed for long preamble bit 3 of CR5 selects CR36 or CR 37 CONFIGURATION REGISTER ADDRESS 37 (4Ch) R/W SCRAMBLER SEED SHORT PREAMBLE Bit 7 Bit 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. scrambler seed for short preamble bit 3 of CR5 selects CR36 or CR 37 CONFIGURATION REGISTER ADDRESS 38 (4Eh) R/W ED THRESHOLD Bit 7:0 Energy detect threshold CONFIGURATION REGISTER ADDRESS 39 (50h) R/W CMF GAIN THRESHOLD Bit 7:0 Channel Matched filter gain threshold CONFIGURATION REGISTER ADDRESS 48 (60h) R/W SQ1 SCALE FACTOR Bit 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. SQ1 scale factor (0-4 range) (000000 - 100000) CONFIGURATION REGISTER ADDRESS 50 (66h) R TEST BUS READ Bit 7:0 reads value on test bus CONFIGURATION REGISTER ADDRESS 51 (68h) R SIGNAL QUALITY MEASURE Bit 7:0 measures signal quality based on the SNR in the carrier tracking loop CONFIGURATION REGISTER ADDRESS 52 (6Ah) R RECEIVED SIGNAL FIELD Bit 7:0 8-bit value of received signal field
Bit 2
Bit 1
Bit 0
29
HFA3861
CONFIGURATION REGISTER ADDRESS 53 (6Ch) R RECEIVED SERVICE FIELD Bit 7:0 8-bit value of received service field CONFIGURATION REGISTER ADDRESS 54 (6Eh) R RECEIVED LENGTH FIELD, LOW Bit 7:0 8-bit value of received length field, low byte CONFIGURATION REGISTER ADDRESS 55 (70h) R RECEIVED LENGTH FIELD, HIGH Bit 7:0 8-bit value of received length field, high byte CONFIGURATION REGISTER ADDRESS 56 (72h) R CALCULATED CRC ON RECEIVED HEADER, LOW Bit 7:0 8-bit value of CRC calculated on header, low byte CONFIGURATION REGISTER ADDRESS 57 (74h) R CALCULATED CRC ON RECEIVED HEADER, HIGH Bit 7:0 8-bit value of CRC calculated on header, high byte CONFIGURATION REGISTER ADDRESS 58 (74h) R TX POWER MEASUREMENT Bit 7:0 8-bit value of transmit power measurement (-128 to 127 range) CONFIGURATION REGISTER ADDRESS 59 (78h) R RX MEAN POWER Bit 7:0 Average power of received signal after log table lookup (0-255 range) CONFIGURATION REGISTER ADDRESS 60 (7Ah) R RX_IF_AGC Bit 7 Bits 6:0 unused AGC output to the DAC, MSB unused CONFIGURATION REGISTER ADDRESS 61 (7Ch) R RECEIVE STATUS Bit 7:5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 unused ED, energy detect past threshold TX PWR det Reg semaphore - a 1 indicates CR58 has updated since last read AGC lock - a 1 indicates AGC is within limits of lock window CR20 hwStopBHit - a 1 indicates rails hit, AGC updates stopped RX_RF_AGC - status of AGC output to RF chip CONFIGURATION REGISTER ADDRESS 62 (7Eh) R RSSI Bit 7:0 8-bit value of RSSI CONFIGURATION REGISTER ADDRESS 63 (80h) R CALCULATED CRC ON RECEIVED HEADER, HIGH Bit 7:6 signal field value 00 = 1 10 = 2 01 = 5.5 or 11 SFD found Short preamble detected valid signal field found valid CRC 16 Antenna used on last good packet NA not used
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
30
HFA3861
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 4) JA (C/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.70V to +3.60V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175,000 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 4. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical One Input Voltage Logical Zero Input Voltage Logical One Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance NOTES: 5. Output load 30pF.
VCC = 3.0V to 3.3V 10%, TA = -40oC to 85oC SYMBOL ICCOP ICCSB II IO VIH VIL VOH VOL CIN COUT TEST CONDITIONS VCC = 3.6V, CLK Frequency 44MHz (Notes 5, 6) VCC = Max, Outputs Not Loaded VCC = Max, Input = 0V or VCC VCC = Max, Input = 0V or VCC VCC = Max, Min VCC = Min, Max IOH = -1mA, VCC = Min IOL = 2mA, VCC = Min CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC, Note 6 MIN -10 -10 0.7 VCC VCC -0.2 TYP 100 0.5 1 1 .2 5 5 MAX 120 1 10 10 VCC /3 0.2 10 10 UNITS mA mA A A V V V V pF pF
6. Not tested, but characterized at initial design and at major process/design changes.
AC Electrical Specifications
PARAMETER MCLK Period MCLK Duty Cycle Rise/Fall (All Outputs) TX_PE to IOUT/QOUT (1st Valid Chip) TX_PE Inactive Width TX_CLK Width Hi or Low TX_RDY Active to 1st TX_CLK Hi Setup TXD to TX_CLK Hi Hold TXD to TX_CLK Hi TX_CLK to TX_PE Inactive (1Mbps) TX_CLK to TX_PE Inactive (2Mbps) TX_CLK to TX_PE Inactive (5.5Mbps) TX_CLK to TX_PE Inactive (11Mbps)
VCC = 3.0V to 3.3V 10%, TA = -40oC to 85oC (Note 7) MCLK = 44MHz SYMBOL tCP MIN 22.5 40/60 tD1 tTLP tTCD tRC tTDS tTDH tPEH tPEH tPEH tPEH tRI 2.18 2.22 40 260 30 0 0 0 0 0 -20 MAX 60/40 10 2.3 965 420 160 65 800 UNITS ns % ns (Notes 8, 9) s (Notes 8, 10) s (Notes 8, 11) ns ns ns ns ns (Notes 8, 19) ns (Notes 8, 19) ns (Notes 8, 19) ns (Notes 8, 19) ns
TX_RDY Inactive to Last Chip of MPDU Out
31
HFA3861
AC Electrical Specifications
PARAMETER TXD Modulation Extension RX_PE Inactive Width RX_CLK Period (11Mbps Mode) RX_CLK Width Hi or Low (11Mbps Mode) RX_CLK to RXD MD_RDY to 1st RX_CLK RXD to 1st RX_CLK Setup RXD to RX_CLK RX_CLK to RX_PE Inactive (1Mbps) RX_CLK to RX_PE Inactive (2Mbps) RX_CLK to RX_PE Inactive (5.5Mbps) RX_CLK to RX_PE Inactive (11Mbps) RX_PE inactive to MD_RDY Inactive Last Chip of SFD in to MD_RDY Active RX Delay RESET Width Active RX_PE to CCA Valid RX_PE to RSSI Valid SCLK Clock Period SCLK Width Hi or Low Setup to SCLK + Edge (SD, SDI, R/W, CS) Hold Time from SCLK + Edge (SD, SDI, R/W, CS) SD Out Delay from SCLK + Edge SD Out Enable/Disable from R/W TEST 0-7, CCA, ANTSEL, TEST_CK from MCLK NOTES: 7. AC tests performed with CL = 40pF, IOL = 2mA, and IOH = -1mA. Input reference level all inputs 1.5V. Test VIH = VCC , VIL = 0V; VOH = VOL = VCC/2. 8. Not tested, but characterized at initial design and at major process/design changes. 9. Measured from VIL to VIH . 10. IOUT/QOUT are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits. 11. TX_PE must be inactive before going active to generate a new packet. 12. IOUT/QOUT are modulated after last chip of valid data to provide ramp down time for RF/IF circuits. 13. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition. 14. RX_PE active to inactive delay to prevent next RX_CLK. 15. Assumes RX_PE inactive after last RX_CLK. 16. MD_RDY programmed to go active after SFD detect. (measured from IIN , QIN). 17. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at IIN , QIN to MD_RDY active. 18. Minimum time to insure Reset. RESET must be followed by an RX_PE pulse to insure proper operation. This pulse should not be used for first receive or acquisition. 19. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within 40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns. tRPW tCCA tCCA tSCP tSCW tSCS tSCH tSCD tSCED tD2 VCC = 3.0V to 3.3V 10%, TA = -40oC to 85oC (Note 7) (Continued) MCLK = 44MHz SYMBOL tME tRLP tRCP tRCD tRDD tRD1 tRD1 tRDS tREH tREH tREH tREH tRD2 tRD3 MIN 2 70 90 44 25 940 940 31 0 0 0 0 5 2.77 2.77 50 90 20 30 0 MAX 60 925 380 140 50 30 2.86 2.86 16 16 30 15 40 UNITS s (Notes 8, 12) ns (Notes 8, 13) ns ns ns ns (Notes 8, 16) ns ns ns (Notes 8, 14) ns (Notes 8, 14) ns (Notes 8, 14) ns (Notes 8, 14) ns (Note 15) s (Notes 8, 16) s (Notes 8, 17) ns (Notes 8, 18) s (Note 8) s (Note 8) ns ns ns ns ns ns (Note 8) ns
32
HFA3861
I and Q A/D AC Electrical Specifications
PARAMETER Full Scale Input Voltage (VP-P) Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) NOTE: 20. Not tested, but characterized at initial design and at major process/design changes. (Note 20) MIN 0.25 5 TYP 0.50 20 5 MAX 1.0 22 UNITS V MHz pF k MHz
Test Circuit
DUT CL (NOTE 21) IOH 1.5V IOL (NOTE 22) S1
EQUIVALENT CIRCUIT
NOTES: 21. Includes Stray and JIG Capacitance. 22. Switch S1 Open for ICCSB and ICCOP . FIGURE 16. TEST LOAD CIRCUIT
Waveforms
tSCP tSCW SCLK tSCS SDI, R/W, SD, CS tSCD SD (AS OUTPUT) R/W tSCH tSCW
SD tSCED tSCED
FIGURE 17. SERIAL CONTROL PORT SIGNAL TIMING
33
HFA3861 Waveforms (Continued)
tTLP
TX_PE tDI IOUT, QOUT tRI TXRDY TX_CLK TXD tTDS tTDH tRC tTCD tTCD tPEH tME
FIGURE 18. TX PORT SIGNAL TIMING
tRLP RX_PE tRD3 tREH IIN, QIN MD_RDY RX_CLK RXD tCCA tRCD tRD2 tRCP
tRCD tRD1 tRDD tRDS
CCA, RSSI
NOTE:
RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. RSSI Output on TEST (5:0). FIGURE 19. RX PORT SIGNAL TIMING
MCLK tD2 TEST 0-7, CCA, ANTSEL, TEST_CK
RESET
tRPW
MCLK
tCP
FIGURE 20. MISCELLANEOUS SIGNAL TIMING
34
HFA3861 Thin Plastic Quad Flatpack Packages (TQFP)
D D1 -D-
Q64.10x10 (JEDEC MS-026ACD ISSUE B)
64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 A2 MIN 0.002 0.038 0.007 0.007 0.468 0.390 0.468 0.390 0.018 64 0.020 BSC MAX 0.047 0.005 0.041 0.010 0.009 0.476 0.397 0.476 0.397 0.029 MILLIMETERS MIN 0.05 0.95 0.17 0.17 11.90 9.9 11.9 9.9 0.45 64 0.50 BSC MAX 1.20 0.15 1.05 0.27 0.23 12.10 10.10 12.10 10.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- .
0.08 M C A-B S 0.003 DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING
-AE E1
-B-
b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.08 0.003 -C-
E1 L N e
-H-
4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 A2 A1
11o-13o
0.09/0.20 0.004/0.008
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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